A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm

Leakage power has become an important component of the total power consumption in FPGAs as process technology shrinks. In addition, a significant amount of leakage power in FPGAs is consumed by the routing resources. Therefore, leakage power reduction in FPGAs should begin with the routing resources. In this paper, we propose a novel directional coarse-grained power gating architecture for switch boxes. In addition, the existing VPR routing algorithm has been adapted with a new cost function to support the new power gating architecture. Results have shown that the new cost function yields an average improvement of 22% as compared to the existing VPR cost function in terms of the number of power gating regions that can be turned off.