A systems approach to gate CD control: metrology, throughput, and OEE

The 0.13 /spl mu/m semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures as small as 100 nm, creating a demand for 10 nm gate linewidth control and for measurement precision on the order of 1 nm. In this work, we show that the prospects are excellent for using CDSEM technology to control gate linewidths with 1 nm precision, very high effective throughput, and 75% overall equipment effectiveness in 300 mm factories.