Design of data format converters using two-dimensional register allocation

In many DSP applications, data format converters (DFC's) are used to permute the data transferred between processing modules. In VLSI implementations, these converters consume a large amount of the given resources, especially area. Previous methods on the synthesis of data format converters have focused on optimizing the number of registers. Also, two-dimensional register allocation schemes have been proposed to reduce the area of the DFC's. In this work, we present another two-dimensional register allocation scheme where the aim is to optimize the number of registers as well as reduce the number of interconnections by maximizing the reuse of the interconnections previously made during the synthesis procedure. Such a strategy also leads to a reduction in the number of multiplexers used. We show, using automated layout results, that the proposed allocation scheme results in lower area DFC's than the previously proposed ones.