Gate bounded diode triggered high holding voltage SCR clamp for on-chip ESD protection in HV ICs

Gate bounded diode triggered high holding voltage SCR ESD clamp for high voltage application is proposed in this paper. A straight-forward gate bounded diode for low triggering voltage can be implemented by LDMOS modification. The holding voltage of this SCR clamp can be effectively increased for safe operating area by adding a floating diffusion to the LDMOS based LVTSCR. This proposal was verified by TCAD simulation, TLP analysis and ESD test.