Pulse-skipping power factor correction control schemes for AC/DC power converters

Power factor correction (PFC) is a must nowadays for many power supply applications. Recently, there has been a trend to cut down the overall cost even at the expense of the input harmonic current performance, as long as it meets the minimum requirement. There was a strategy reported, the so-called pulse-skipping PFC converter to achieve the goal mentioned above. In this strategy, there are two power stages used, like a conventional PFC circuit, but only one feedback control IC to provide gate drive signals to the main switches of the two stages. The frontstage boost converter is set to always operate in discontinuous conduction mode to achieve acceptable power factor. The second stage is a flyback converter. The gate drive signal to the flyback converter is derived with a conventional PWM strategy, but a pulse-skipping technique is applied to the aforementioned gatedrive signal to drive the boost converter stage. This control strategy can reduce the switching losses of the front stage, manage the interlink bulk capacitor voltage to stay within reasonable range, and may keep the input harmonic current performance in acceptable range. This paper presents the results of theoretical investigation of such a strategy. Mathematical analyses are conducted to reveal the complicated relationships for design purpose. Simulations are performed to verify the mathematical results. The conclusions indicate that there are advantages of such an approach for applications where hold-up time is not required, such as a driver circuit for LED lighting.