Si based tunneling field effect transistors and inverters

Reducing the drain voltage, V
_DD
, is the key leverage to lower power dissipation in circuits, since the dynamic losses increase proportional to V
_DD2
multiplied by the frequency. Presently, fully depleted silicon on insulator (FDSOI) technology sets the level pole for ultra-low power applications: At 0.6 V a clock frequency of 1 GHz has been achieved [1]. A further reduction of V
_DD
limits the performance considerably. IMEC announced an ultralow power chip working at voltages from 1V down to 0.4 V. In the sub-threshold regime at 0.4 V the clock frequency reduces to 1 MHz but also the energy consumption drops to a fraction of standard circuits [2]. Numerous applications are foreseeable for battery-powered and energy scavenging smart devices. The question is will tunnel field effect transistors (TFET) provide superior performance.