Planarized multilevel interconnection using chemical mechanical polishing of selective CVD-Al via plugs

A planarization process for selective CVD-Al via plugs using chemical mechanical polishing (CMP) is proposed and a four-level interconnection system with all stacked via plugs is demonstrated. A Cl/sub 2//Ar post-cleaning treatment after Al plug CMP is shown to be the key process in obtaining excellent via chain characteristics with high yield and small resistance scattering. A sandwich of Ti/TiN/Ti barrier layers with a CVD-Al plug is proved to be one of the best via plug structures because of its low via resistance and high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4-/spl mu/m, equal pitch and four-level interconnection.