Design and measurements results of 7-bit low-power, low area SAR A/D converter for pixel systems

The design and measurements results of analog-to-digital converter implemented in CMOS 180 nm technology have been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications. The presented converter achieves 2.5 MS/s sampling rate with 7-bit resolution at 77 μW and occupies only 90 μm × 95 μm.