A 10-b 100-MSPS low power pipeline ADC for high energy physics experiments

A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 6.9dB signal-to-noise and distorsion ratio (SNDR). 8.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a full-scale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm
²
die area.