Highly parallel architecture for the least mean squares (LMS) algorithm

In this paper, a fast digital implementation for the least mean squares (LMS) algorithm is proposed. The high concurrency of its structure allows for high processing speed with a sampling period of O(log N), where N is the number of filter taps. Chip area is minimized by the use of serial-parallel multipliers. In these multipliers, which use redundant arithmetic, the serial variables are transferred digit by digit, the most significant first.