High-Performance InAs-On-Insulator n-MOSFETs With Ni-InGaAs S/D Realized by Contact Resistance Reduction Technology

We have systematically analyzed the components of source/drain (S/D) resistance (RSD) in InGaAs n-MOSFETs with Ni-InGaAs metal S/D. It is found that Ni-InGaAs has a low resistivity of ~250 μΩ·cm in a thickness of Ni-InGaAs (T
_Ni-InGaAs
) of down to ~4 nm. Contact resistance between the contact pads and Ni-InGaAs (R
_C
) is found to be the most dominant component of R
_SD
in control InGaAs MOSFETs, because of the existence of Ni oxides. By developing a surface cleaning process using NH
₄
OH and H
₂
plasma for Ni-InGaAs surfaces, we have reduced R
_C
down to 11 Ω·μm without any accompanying drawbacks. Also, the increase in the channel indium (In) content has provided further R
_SD
reduction. Employing these R
_SD
reduction technologies, we present 20-nm-channel length (L
_ch
) InAs-on-insulator n-MOSFETs on Si substrates with Ni-InGaAs metal S/D. The devices provide a high maximum ON-current (ION) and maximum transconductance (G
_m
) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (V
_D
) of 0.5 V. This high performance is attributable to the low R
_SD
realized by the surface cleaning process of Ni-InGaAs surfaces before the contact pad formation as well as the increase in the In content in the channel layer. Furthermore, it is found that the interface resistance (R
_interface
) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing the In content in the channel layers.