Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-μm CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.