Vertical polysilicon Pinch-Off FET for 3D memory technology: Feasibility and electrical performance

The feasibility of a vertical polysilicon Pinch-Off FET (POFET) for application in 3D memory technology is demonstrated. The proposed device is fully compatible with the standard punch-and-plug process, as required for bit cost scaling. We show that the depletion mode POFET cell with an optimized n-doping level, fabricated in our 3D-SONOS test vehicle has a significantly higher read current than conventional undoped poly-Si inversion mode device. Furthermore, the implications of different ONO thicknesses in the memory performance are analyzed and discussed into detail.