A novel multilayer Inter-Gate Dielectric enabling up to 18V Program / Erase window for planar NAND flash

The required transition from Control Gate wrap-around to planar structure for NAND flash scaling below 20 nm node causes important loss of coupling factor. In order to recover the Program / Erase window, a Hybrid Floating Gate featuring a high work function metal on top of Si, together with a high-k Inter-Gate Dielectric are needed. In this paper, we develop a multilayer Inter-Gate Dielectric based on HfAlO and Al
₂
O
₃
, combined with a Si/TiN Hybrid Floating Gate. By optimizing the stack structure, a window as large as ~18V could be obtained.