Dual-VCC 8T-bitcell SRAM Array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range

A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. V
_MIN
limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-V
_MIN
. Measurements show 130-270mV lower VMIN with 27-46% lower power at 0.4-1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.