Implementation of I2C master bus controller on FPGA

This paper implements serial data communication using I
²
C (Inter-Integrated Circuit) master bus controller using a field programmable gate array (FPGA). The I
²
C master bus controller was interfaced with MAXIM DS1307, which act as a slave. This module was designed in Verilog HDL and simulated in Modelsim 10.1c. The design was synthesized using Xilinx ISE Design Suite 14.2. I
²
C master initiates data transmission and in order slave responds to it. It can be used to interface low speed peripherals like motherboard, embedded system, mobile phones, set top boxes, DVD, PDA's or other electronic devices.