Analysis of a class of decimated clock/data recovery architectures for serial links

This paper analyzes the performance of a class of decimated clock data recovery (CDR) architectures for serial links. Jitter tolerance is obtained analytically following a derivation of the phase detector (PD) gain for sinusoidal jitter and a derivation of the CDR linear transfer function. A methodology is proposed to perform the analysis iteratively with a dynamic PD gain. The analysis is shown to correlate well with time step simulation results which simulate the non-linear behavior of the PD. Analysis results are presented for multiple decimation factors.