A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators

This paper presents the design of an fully differential current steering DAC for a continuous time (CT) ΔΣ modulators with an all native switched DAC cell. In using the proposed cell a lower load capacitance on the virtual ground node of the integrator, reduced charge injection and clock feed-through is obtained when compared to the commonly used NMOS/PMOS DAC cell, thus resulting in an improved performance and lower ISI sensitivity. The native switched DAC is functionally demonstrated within a third order CT ΔΣ modulator operating at an f
_S
of 1GHz with an OSR of 20. The schematic based DAC is designed in a 1.2V 90nm TMSC process including V-I biasing to track the modulator input resistance. Within the explemary ΔΣ modulator an SNDR of 79.12dB and SFDR of 93.44dB within a 25MHz bandwidth is achieved while only being limited by the thermal input noise of the modulator. When comparing to the commonly used NMOS/PMOS switched cell, an improvement of 3dB and 7.3dB in SNDR and SFDR is achieved with the same area and current.