VHDL synthesizable hardware architecture design of back propagation neural networks

Evolutionary Algorithms (EA) are used in many optimization problems such as the Artificial Neural Networks (ANN). But the main challenging issue of using these algorithms is the time taken for computing the function value, implementation and verification of hardware architecture design. In this paper we propose to implement the architecture design of Back Propagation Neural (BPN) networks using Very High Speed Integrated Circuits Hardware Description Language (VHDL). The simulation is carried out using Xilinx Spartan 3E.