Indirect-Feedback Sigma-Delta Image Sensors: Theory, Modeling and Design

A novel architecture for a CMOS image sensor that incorporates a column-level sigma-delta (ΣΔ) analog-to-digital converter is presented. An indirect-feedback readout architecture where the digital output of the ΣΔ modulator is accumulated by a digital counter and converted to an analog voltage that serves as the reference voltage in the modulator's comparator is employed. A time-domain pixel simulator that enables assessment of the major noise contributions in this type of imager is also presented. Theoretical calculations agree with simulation results, showing a minimum readout noise of 2.18e- and a dynamic range (DR) of over 100 dB. Prototype chip tests without multiple resets show an 87 dB dynamic range with a readout noise of 2.17e-.