8-bit folding ADC based on switched capacitor

This paper presents an 8-bit folding analog-digital converter (ADC) using switched capacitors. In this architecture, the conversion is achieved when the signal crosses a determined voltage level and at this time, a voltage value is added or subtracted from the analog input signal. The ADC proposed consists of eight identical stages that perform the conversion of one bit at a time. Each stage consists of an amplifier circuit with a gain of 2 using switched capacitor. The ADC is designed in 0.35 μm CMOS standard technology. When supplied with 3.3 V, the proposed ADC consumes a power of 2.5 mW and presents the following results: conversion time of 100 ns and 45.8 dB of SNDR (Signal to noise plus distortion ratio).