Digital methods of offset compensation in 90nm CMOS operational amplifiers

This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.