A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs

A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (/spl plusmn/0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of /spl plusmn/0.7 dB and /spl plusmn/0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125/spl deg/C is /spl plusmn/1.05 dB which is an increase of /spl plusmn/0.35 dB over a 100/spl deg/C range.