A 6.25Gbps Feed-forward Equalizer in 0.18μm CMOS Technology for SerDes

This paper presents a 6.25Gbps feed-forward equalizer (FFE) to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane. The 3-tap fractionally spaced equalizer consists of a delay line, multiplier & summer cells and an output circuit. Active-inductive peaking circuit and capacitor-degenerated circuit are used in the delay line and the output stage respectively to meet the bandwidth demand. The proposed FFE has been implemented in TSMC 0.18μm CMOS technology with a whole area of 0.5mm×0.51mm including I/O pads. The power consumption of the core circuit is 31.7mW under 1.8V power supply. Post simulation results show that the distorted signal through a 24-inch backplane is well recovered by this equalizer.