Evaluation of logic SER for a network processor and the use of targeted hardening to improve system SER performance

Chip-level logic masking simulations were performed on a network processor with ~1.75M flip-flops to identify the masking factors and the functional blocks that contribute to most errors. Results indicate that most errors originate from a few functional blocks, and that targeted hardening of the flip-flops can significantly improve the overall system SER at very low area, speed, and power penalties. A novel hysteresis-based DFF hardening technique is presented with experimental results from a 28 nm test chip design.