A compact SPICE model for statistical post-breakdown gate current increase due to TDDB

We developed a compact SPICE model capable of modeling the increases in post-breakdown (BD) gate current (I
_{G_BD}
) due to time-dependent dielectric breakdown (TDDB), for circuit level simulations. I
_{G_BD}
is determined by the random shape of the BD path given by the percolation model and the location of BD path. The statistical nature of our analysis provides different I
_{G_BD}
for each transistor and hence, can be efficient for statistical circuit simulation. The generated gate current is fed into the proposed SPICE model incorporating transistor threshold voltage shift (V
_TH-SHIFT
) due to bias temperature instability (BTI). We present simulation results of a ring oscillator using our model and compare the results to experimental data from an ultrathin CMOS technology. We also show that IDDQ is a more representative signature of TDDB degradation than the delay of a ring oscillator.