Prediction table based management policy for STT-RAM and SRAM hybrid cache

STT-RAM has emerged as one of the most promising candidates for future on-chip cache due to STT-RAM's high density and low leakage. However, the STT-RAM has many disadvantages, such as: high write energy and long writing latency. To alleviate the problems, many STT-RAM and SRAM hybrid cache architectures have been proposed. In this paper, we propose a prediction table based hybrid L2 cache management policy named PTHCM. By adding a prediction table to the hybrid cache, the access information of each cache line can be recorded and we can predict the cache lines that have become dead in SRAM, lines that will be less-written and frequently-written in advance. Based on these information provided by prediction table, we propose a new cache replacement and management policy for hybrid cache architecture which replaces the dead cache lines in SRAM to improve the utilization ratio of SRAM, places frequently-written lines into SRAM and swaps out less-written lines from SRAM as early as possible. Compared with a baseline hybrid cache design, our design reduces 23.3% of the write operations to STT-RAM, and achieves 8.2% power reduction.