Impact of encroaching length and taper on double gate tunnel FET performance using TCAD simulations

A double gate Tunnel FET structure with taper at the source-channel junction with source region encroaching further into the channel is studied using TCAD simulations. The device simulations have been implemented for different taper angles and source encroachment length, and the transfer characteristics (I
D
-V
G
) are studied. An optimum taper angle is seen for the device with a particular source encroachment length, considering the drive current (I
ON
) as metric.