A novel low power 8T-cell sub-threshold SRAM with improved read-SNM

The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is simple. The new structure uses fewer controlling signal in comparison to the conventional 8T-cell SRAM. Thus, the proposed 32k SRAM consumes 25% lower power consumption in the read operation for 0.3V sub-threshold SRAM in 90nm TSMC CMOS model.