Measurement of back end of line thermal resistance for 3D chip stacks

The thermal resistances of thirty-nine different back end of line (BEOL) test sites consisting of four line levels and three via levels in SiCOH were measured. The measured unit resistance values ranged from 0.5 to 5.5 C-mm
²
/W. The percent via area was varied from 0.31 to 6.25 %, the percent line area from 17 to 67%, the configuration of the vias, the distance between vias, and the line and via pitch were also varied. The measured values were compared to results from an internally developed electromagnetic simulation tool, ChipJoule. Comparison of the simulations with measured values validated the ChipJoule tool, which can be used to simulate full BEOL structures using mask design data.