A Successive Approximation A/D Converter Using a PWM Modulator DAC

This paper presents a new SAR A/D conversion architecture that uses a PWM modulator and a first order low pass filter as alternative to conventional DAC implementations. Design equations were derived and a circuit implementation is proposed. In order to validate the proposed architecture, a 4bit successive approximation A/D converter has been designed and simulated. Then the circuit layout was developed in 0.5u m CMOS process with CADENCE Virtuoso. Post layout simulations were performed using BSIM3v3 model in Spectre simulator. DNL and INL erros are less then 0.1LSB. The power consumption is only 16u W for a 2.5V power supply.