Impact of design engineering on RF linearity and noise performance of nanoscale DG SOI MOSFETs

The influence of different design engineering on linearity and noise performance of nanoscale double gate MOSFETs is analyzed using TCAD device simulations. We observe that graded channel (GC) architecture improves the RF linearity and noise performance of DG MOSFETs when compared with dual material gate (DMG) engineering. The performance of DMG devices is comparable to GC only for longer channel lengths. The combination of GC and DMG, i.e. Graded channel dual material gate (GCDMG) outperforms other device configurations over a wide range of scaling.