Low power low voltage wide frequency resonant clock and data circuits for power reductions

Driver circuits that save global clock and data switching power by 25% or more using LC resonance for energy recovery are shown. A 10x operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance operation is used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2nH range are sufficient. The design is readily scaled from 90nm to 45nm in standard CMOS processes and is robust with 50% variation in component values. The resulting power savings add up to 10's of watts in high performance processors.