Reconfigurable encryption system: Encrypt digital data

This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.