A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process

This paper presents a high-throughput BCH decoder that can correct 100 bit-errors. Several optimization methods are proposed to reduce the hardware complexity caused by the large error-correction capability. Based on the proposed methods, an 8-parallel decoder is designed for the (9592, 8192, 100) BCH code, which achieves a decoding throughput of 3Gb/s and occupies 2.08mm
²
in 0.13µm CMOS process.