Pre- and post-thinning silicon thickness mapping using a high throughput defect inspection system for advanced 3D IC packaging

Stacked ICs (SIC) with direct connecting using TSV are becoming increasingly important over conventional ICs to further achieve device shrinkage. One of the key enabler for the volume ramp for 3D SICs is the availability of a fast, mature and reliable metrology for advanced process control (APC). In today's via-first and via-middle TSV process flows, the TSVs are formed in the device layer. The wafer is then flipped and temporarily bonded to a carrier substrate for backside thinning. One of the metrology challenges in the wafer packaging process is to accurately measure and monitor the Silicon Thickness over the TSV pre- and post-thmmng. During the wafer thinning by grinding control of the Residual Si Thickness (RST) can be used to prevent premature exposure of the TSVs. Poor RST monitoring and subsequent lack of process control can lead to a significant yield loss should the copper nails be exposed during grinding' After the grinding process on the device wafer, typically anywhere between 1 to 15 microns of silicon remains over the vias. In a typical process, the vias are then exposed by a combination of wet etch, CMP and/or plasma etching processes. In case of excessive thinning the residual silicon thickness is too thin resulting in exposed copper nails, via corrosion and via damage during these processes.