Silicon wafer thinning and backside via exposure by wet etching

In this study, we developed silicon wafer thinning and backside via exposure by wet etching for low-cost, damage-less through silicon via (TSV) formation. Silicon wafer thinning down to approximately 50 μm was carried out using a highly concentrated HF/HNO
₃
solution, and backside via exposure was carried out using an alkaline solution (accelerator-added KOH solution), without damaging the TSV liner oxide. The Si etching rates of these processes were 600-800 μm/min and 4 μm/min (at 75 °C), respectively. We also evaluated the damage to the silicon surface and TSV after these processes. The observations using an optical microscope, a transmission electron microscope (TEM), and a scanning electron microscope (SEM) showed that no damage layers were formed at the Si surface or TSVs. In addition, the leakage current between the TSVs was found to be very small.