Improved low-cost FPGA image processor architecture with external line memory

Today's FPGAs are capable of performing complex Image Processing schemes. For large images the limiting factor is the size of the line memory required, especially in lower cost FPGAs. In this paper we introduce an FPGA-based architecture for Pipelined Image Processor that utilizes external line memory. We describe the suggested architecture, explain the reasoning behind it and give the guidelines to achieve the best efficiency possible. We define efficiency as performing the desired calculation using the minimal hardware configuration. Thus we give the tools to design minimal hardware configurations. The principle of the suggested architecture is based on minimal data transportation between the external line memory and the FPGA. While the original architecture presented in a recent paper addressed the case of equal line size in all Processing Elements the improved architecture presented in this paper is capable of handling scaling, i.e., changing the line size and the number of lines at any location in the IP chain.