Implementation of low power MB-OFDM PHY baseband modem with parallel architecture

The multi-band orthogonal frequency division multiplexing modem needs to process large amount of computations in short time for support of high data rates from 53 to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi way parallel architecture has been proposed. In this paper introduced several novel optimization techniques for resource efficient implementation of the baseband modem which has 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization techniques could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of entire baseband modem were about 474 kgates and 248 mW at 66 MHz.