Manufacturing Challenges of GaN-on-Si HEMTs in a 200 mm CMOS Fab

In this paper, we report on the challenges related to growth and processing of 200 mm GaN-on-Si wafers in a CMOS fab. We describe the Au free process we developed as well as how we assure wafer quality prior processing. For the first time, we analyze possible Ga contamination issues related to the processing of GaN wafers and we present the cleaning procedures we developed to avoid it.