Novel hardware implementation of LLR-based non-binary LDPC decoders

Binary Low Density Parity Check (LDPC) codes are known to have performance approaching capacity utilization for large block lengths. For short and medium term block lengths, the codes have lower capacity utilization and poorer BER performance due to cycles in the codes. The non-binary LDPC codes have started attracting attention for short and medium length code implementations, which is a requirement for standards like Wi-Fi applications. Current implementations of non-binary LDPC codes focus on serial or partly parallel implementation due to hardware complexity and chip size. We propose a fully parallel implementation for two algorithms. The algorithms are the SPA algorithm with max* function and a sub-optimal form of this called as max implementation. The max implementation has a lower hardware cost and a low performance penalty. The area of sub-optimal max implementation is almost 32% less than that of max implementation. The clock for max is faster by 33%, as a result it has low latency and high throughput as compared to max* algorithm.