Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

Trap density (D
_it
) was extracted for the first time in 3-D stacked NAND flash memory with the tube-type poly-Si channel structure. We verified extracted D
_it
with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory device. In 3-D stacked NAND flash memory device, the D
_it
extracted by conductance method was 1~2×10
¹²
cm
^-2
eV
^-1
in E
_c
-E
_T
of 0.15~0.35 eV. The simulation results of I
_BL
-V
_CG
and C-V
_CG
based on the D
_it
were conformable with the measurement data. Then we investigated the effects of program/erase (P/E) cycling stress on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.