Parametric study, modeling of etching process and application for tapered through-silicon-via

Tapered TSV interconnection has begun used in CMOS Image Senor (CIS) and currently is penetrating its application in other areas, such as MEMS devices and Si Interposer. It helps relive the technical difficulties of conformal deposition of insulation layer and conducting layer and therefore it's helpful for yield improvement and cost reduction. Besides that, it helps also relieve the stress accumulation at the opening of TSV which poses a potential threat to reliability. In this paper, parametric study of etching process for tapered TSV with SF
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will be carried out in an STS ICP etching machine. Interactions between the process parameters and TSV profile will be studied and TSV profile development versus time will be modeled for offering guidance for TSV profile design and its relative etching recipe design/optimization. Finally, in order to extend SF
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etching technique's capability in producing high depth, no sidewall bowing TSV, a manufacturing method featuring in a SF
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F
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etching followed by a BOSCH process will be proposed, and recipe design/optimization and its verification for a designed tapered TSV will be detailed.