Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces

In this paper we analyze the impact of power supply noise on clock jitter in high-speed DDR memory interfaces. Random system failures on a custom IC were traced to excessive clock jitter on the DDR output clock, which when debugged were attributed to power supply noise caused at certain frequency bands (between ~30 and ~100MHz). We present methods that have been used at the architectural and system levels and in physical design to alleviate the effect of the supply noise on the DDR clock.