Virtual shared memory architecture for inter-task communication in partial reconfigurable systems

This paper presents a virtual shared memory architecture for inter-task communication in partial reconfigurable systems. The hardware tasks communicate with each other using the same content shared by physically separated Block RAMs (BRAMs). The coherence of the content is ensured by the Internal Configuration Access Port (ICAP), rather than conventional on-chip logic. The benefit of this approach resides in the flexibility of partial task reconfiguration that results from the ICAP-based synchronization mechanism, allowing hardware tasks to behave like software tasks, as they can be swapped in/out of the chip arbitrarily without any area boundary constraints. Moreover, a fast synchronization method which uses compressed bitstream is presented in this paper. The result shows significant improvements in synchronization speed at a low area overhead.