Indigenous development of SERDES interface for miniaturization

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. Conventional parallel data transmission requires a large number of cables/interface-packages and results in large weight and volume. Parallel interface in a typical future camera system requires >8000 cables between camera electronics and data handling system. In addition, with increase in transmission rate, problems associated with crosstalk become more critical. One possible solution identified is serial interface, also termed as SERDES (Serializer/DESerializer) interface. A typical SERDES interface comprises of encoder/decoder, PLL, timing-control and multiplexer/de-multiplexer. Encoding of serial data solves high speed serial data transmission problems by incorporating clock embedding, DC balancing, sync info insertion and error detection. DC balancing also solves the issue of Inter-Symbol Interference (ISI). Available SERDES interface devices have limitations like poor reduction factor, no clock embedding or non-availability of space qualified part. Hence, an attempt is made to understand and implement this interface with a goal of indigenous SERDES ASIC development, which will also overcome the above issues. Various serial encoding techniques are surveyed and 8B/10B encoding technique is finalized for very high speed serial data transmission. As an initial step, 8B/10B encoding based SERDES interface is implemented in a FPGA. Final serial data rate achieved is 250Mbps, which corresponds to transmission of 8-bit at 25MSPS and reduces interfaces by a factor of 8. Higher factors will be achieved by design with new encoding techniques like 12B/14B. This paper discusses different SERDES interfaces, comparison of encoding techniques, FPGA design aspects and test results.