Highly digitalized Flash analog to digital (FADC) converter using Mux based decoder topology

In this paper Flash ADC (FADC) is Implemented in 0.18 μm technology using CMOS Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design of low power high speed FADC. Presence of bubble error reduces output correction capability. An advanced scheme is proposed for correction of bubble error in Mux based decoder. FADC comparators designed with systematic sizing of transistors where linearity measures of convertor include 0.42 LSB INL, +0.62/-0.75 LSB DNL and ENOB 3.09 at 20 MHz.