Optimized AES algorithm using Galois field multiplication and parallel key scheduling

With the advent in computer technology & internet millions of people can communicate with each other so, the information security need has increased greatly. Advance Encryption Standard is latest standard of cryptography and is becoming popular. Since the debut of the Advanced Encryption Standard (AES), it has been thoroughly studied by hardware designers with the goal of reducing the area and delay of the hardware implementation of this cryptosystem. This paper proposes an implementation of the AES mix column and key expansion with area minimization as a goal. Also the simulation result for the different techniques are discussed and compared in this paper. For that Xilinx 9.2i tool is used. Based on simulation results, a few coding methodologies are discussed. We show that our design has lower resource utilization than other designs that implement both the forward and the inverse mix columns operation.