Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies

Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.