A 24-GHz fully integrated phase-locked loop for 60-GHz beamforming

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of -85dBc/Hz in band and -112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm
²
and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.